1. Field of the Invention
The present invention relates to an optical disk device for recording/reproducing data to/from an optical disk.
2. Description of the Related Art
As is known in the art, an optical disk which can be recorded/reproduced includes a plurality of tracks. Each track is further divided into a plurality of sectors, and data is recorded/reproduced to/from the disk by sectors. The data recording/reproduction operation is often performed while the disk is rotated at a constant number of rotations, or a constant rotational velocity (CAV: Constant Angular Velocity). For example, wobbling of the tracks on the optical disk is detected so as to produce a wobble signal which has a cycle corresponding to the number of rotations of the optical disk. Based on the wobble signal, a constant number of rotations of the optical disk is reached, after which data is recorded/reproduced to/from the disk in synchronization with a reference clock signal.
Hereinafter, conventional disk recording/reproduction devices will be described.
FIG. 6 is a block diagram illustrating a conventional disk recording/reproduction device. Referring to FIG. 6, the disk recording/reproduction device includes: a motor 101; an optical disk 102; an optical head 103; a reproduced signal/servo signal detection circuit 104 for producing a reproduced signal, a focusing error signal and a tracking error signal from an output signal of the optical head 103; a reproduced signal digitization circuit 105 for digitizing the reproduced signal; a demodulator 106 for generating reproduced data by demodulating the digitized reproduced signal; a laser drive circuit 107 for driving a laser as a light source for the optical head 103; a recording signal generation circuit 108 for generating, from the modulated data, a signal for optically modulating laser light by the laser drive circuit 107; a modulator 109 for generating a signal for the recording signal generation circuit 108 by modulating data to be recorded; a focusing/tracking control section 110 for controlling the motor 101 and the optical head 103 using the servo signal from the reproduced signal/servo signal detection circuit 104; a reference clock generator 111 for generating a reference clock signal which is used to generate various gate signals needed for recording/reproducing data; a gate signal generator 112 for generating the various gate signals based on the reference clock signal from the reference clock generator 111; an error corrector/address detector 123 for correcting errors in the reproduced data which has been demodulated by the demodulator 106 and for detecting an address from this data; a bias circuit 124 for generating bias voltages; a comparator 125 for comparing the tracking error signal output from the reproduced signal/servo signal detection circuit 104 with the bias voltages generated by the bias circuit 124 so as to detect an abnormal jump; and a number-of-rotation error detection circuit 126 for detecting the number of rotations of the motor 101 by using the reference clock signal.
In the disk recording/reproduction device having such a structure, data is read out from the optical disk 102 using the optical head 103 while the optical disk 102 is rotated at a predetermined number of rotations. The reproduced signal/servo signal detection circuit 104 receives an output signal of the optical head 103. Based on the output signal, the reproduced signal/servo signal detection circuit 104 generates a reproduced signal, a focusing error signal and a tracking error signal, and provides these signals to the subsequent processing circuits. The focusing/tracking control section 110 is provided with the focusing error signal and the tracking error signal, and controls the optical head 103 to always follow the skew and/or the eccentricity of the disk. The reproduced signal digitization circuit 105 is provided with a reproduced signal, and the demodulator 106 is provided with the digitized reproduced signal and a read clock signal which is synchronized with the reproduced signal.
The reference clock generator 111 generates a reference clock signal needed for modulating/demodulating data to be recorded/reproduced by this device. The demodulator 106 converts the reproduced signal to reproduced data using the digitized reproduced signal and the read clock signal in accordance with a predetermined demodulation rule. The reproduced data is then output to the error corrector/address detector 123 in synchronization with the reference clock signal. The error corrector/address detector 123 detects the addresses of the track on the optical disk 102 from the reproduced data, and outputs address detection signals. Based on the address detection signal, the gate signal generator 112 generates a gate signal in synchronization with the reference clock. The gate signal indicates the timing of address detection, which is periodically performed by the optical head 103. The gate signal is used when detecting an address or when recording/reproducing data.
When recording data is input to the modulator 109, the modulator 109 modulates the recording data in accordance with a modulation rule. Based on the modulated output, the recording signal generation circuit 108 generates and outputs a signal for optically modulating laser light. Based on the signal from the recording signal generation circuit 108, the laser drive circuit 107 drives a laser light source of the optical head 103 so that laser light is irradiated from the laser light source. Thus, the recording data is written immediately after the address region on the optical disk 102.
The comparator 125 compares the tracking error signal generated by the reproduced signal/servo signal detection circuit 104 with predetermined voltages from the bias circuit 124 so as to detect an abnormal jump.
The number-of-rotation error detection circuit 126 compares the number of rotations (or the rotation cycle) of the motor 101 (indicated by the number-of-rotation detection signal from the motor 101) with the frequency (or the cycle) of the reference clock signal from the reference clock generator 111 so as to determine how close the current number of rotations of the motor 101 is to the intended number of rotations. When the error falls within a predetermined range, the number-of-rotation error detection circuit 126 outputs a recording enable signal which allows the device to perform a recording operation. In response to the recording enable signal, the modulator 109, the recording signal generation circuit 108 and the laser drive circuit 107 can start a recording operation.
The operation of the device having such a structure for reproducing/recording data from/to sectors on the optical disk 102 will be described with reference to the timing diagrams of FIGS. 7A to 7G. Each sector on the optical disk 102 includes an address region, where the address of the sector is recorded, and a data recording region for data recording/reproduction.
The reproduced signal/servo signal detection circuit 104 receives an output signal from the optical head 103. Based on the output signal, the reproduced signal/servo signal detection circuit 104 generates a reproduced signal, as illustrated in FIG. 7A, and a tracking error signal, as illustrated in FIG. 7B.
When the number of rotations of the optical disk 102 is matched with the intended number of rotations, in order to read the address of the target sector K, the read gate signal of FIG. 7C is activated at a timing (c)-1 based on the address detection signal which has been output for the sector previous to the target sector K. The read gate signal is used as, for example, a start signal for a synchronization operation of the PLL (Phase Locked Loop) circuit, which is provided in the reproduced signal digitization circuit 105. In response to the read gate signal, the PLL circuit in the reproduced signal digitization circuit 105 starts a synchronization operation for the digitized reproduced signal, and outputs to the demodulator 106 a digitized reproduced signal and a read clock signal which is synchronized with the reproduced signal.
The demodulator 106 demodulates the digitized reproduced signal from the reproduced signal digitization circuit 105 based on the read clock signal therefrom. The address demodulation is stably performed by minimizing the misdetection of an address by ensuring the synchronization of the address using a demodulation mark gate signal output from the gate signal generator 112.
The demodulated data is sent from the demodulator 106 to the error corrector/address detector 123. The error corrector/address detector 123 detects an address by the reference clock signal. When the address is normally detected, the error corrector/address detector 123 generates and outputs an address detection signal, as illustrated in FIG. 7E. Based on the address detection signal, the gate signal generator 112 activates again the read gate signal of FIG. 7C at a timing (c)-2 in order to perform a read out operation for data recorded following the address region. Herein, four pulses are output as the address detection signal because four pre-pits are recorded as the address of the address region. One or more of the four pre-pits which are detected are used as a reference location for the sectors.
A reproduction operation for recorded data begins when the read gate signal is activated, and the synchronization operation of the PLL circuit in the reproduced signal digitization circuit 105 is started in response to the activation. As described above, the PLL circuit in the reproduced signal digitization circuit 105 performs a synchronization operation for the digitized reproduced signal and outputs to the demodulator 106 the digitized reproduced signal and the read clock signal which is synchronized with the reproduced signal. As described above, the demodulator 106 demodulates the digitized reproduced signal from the PLL circuit based on the read clock signal therefrom. The data demodulation is stably performed by minimizing the misdetection of frame marks by ensuring the frame synchronization with the data to be read out from the optical disk 102 using a mark gate signal for demodulation of FIG. 7D from the gate signal generator 112.
The demodulated data is sent from the demodulator 106 to the error corrector/address detector 123. The error corrector/address detector 123 performs error correction for the data by the reference clock signal.
Herein, the reference clock signal and the read clock signal have substantially the same frequency since the number of rotations of the optical disk 102 is matched with the predetermined number of rotations. Therefore, in data transfer between the demodulator 106 and the error corrector/address detector 123, there will occur no problem, for example, due to shortage in the capacity of the buffer memory in the demodulator 106.
Next, a data recording operation to the optical disk 102 will be described.
In the following description, it is assumed that data is to be recorded to a target sector L.
The modulator 109 modulates recording data, which is obtained by adding an error correction code to the data to be recorded.
In order to read the address of the target sector L, the read gate signal of FIG. 7C is activated at a timing (c)-3 based on the address detection signal which has been output for the sector previous to the target sector L to which data is to now be recorded.
In response to the read gate signal, the PLL circuit in the reproduced signal digitization circuit 105 starts the synchronization operation for the digitized reproduced signal, and detects the address in a manner similar to that in the above-described data reproduction operation. Based on the address detection signal obtained when the address of the target sector L is detected, a modulator activation signal, as illustrated in FIG. 7G, is activated at a timing (g)-1, whereby the modulation operation by the modulator 109 and the operation of the recording signal generation circuit 108 begin simultaneously. The recording gate signal of FIG. 7F is activated at a timing (f)-1 based on the address detection signal. In response to this, the laser drive circuit 107 optically modulates the laser light output from the optical head 103 based on the signal from the recording signal generation circuit 108 so as to record data to the sector L.
Next, the reproduction/recording operation where the number of rotations of the optical disk 102 is not matched with the predetermined number of rotations will be described with reference to FIGS. 8A to 8G.
Based on the address detection signal for the sector previous to the target sector K from which data is to now be reproduced, the read gate signal of FIG. 8C is activated at a timing (c)-1 in order to read the address of the target sector K.
In response to the read gate signal, the PLL circuit in the reproduced signal digitization circuit 105 starts the synchronization operation as described above, and outputs to the demodulator 106 a digitized reproduced signal and a read clock signal which is synchronized with the reproduced signal.
Herein, it is assumed that the number of rotations of the optical disk 102 has deviated off the predetermined number of rotations during a period of time, from the timing of the address detection signal for the previous sector to the timing (c)-1 of the read gate signal of FIG. 8C for reading the address of the target sector K. In such a case, the read gate signal of FIG. 8C and the mark gate signal for demodulation of FIG. 8D are not activated accurately at a timing when the address of the target sector K should be read; for example, only the first two of the four pre-pits (addresses) are read. Based on the read address, the error corrector/address detector 123 generates an address detection signal, as illustrated in FIG. 8E. Based on the address detection signal, the gate signal generator 112 activates again the read gate signal of FIG. 8C at a timing (c)-2 in order to perform a read out operation for data recorded following the address region.
Thereafter, the data demodulation should be stably performed by minimizing the misdetection of a frame mark by ensuring the frame synchronization with the data read out from the optical disk 102 by using the mark gate signal for demodulation of FIG. 8D. However, since the number of rotations of the optical disk 102 has deviated off the predetermined number of rotations, the mark gate signal for demodulation of FIG. 8D is not synchronized with the data read out from the optical disk 102, whereby data cannot be normally reproduced.
Similarly in a recording operation, when attempting to perform a recording operation to the target sector L, since the number of rotations of the optical disk 102 is not matched with the predetermined number of rotations, only the first one of the four addresses of the target sector L is read, for example. In such a case, data will be recorded beyond the target sector L, i.e., in the address region of the next sector.
Moreover, when the optical head 103 abnormally jumps from one track to another due to a shock to the device, for example, such an abnormal jump should be detected. In the conventional device, the abnormal jump is detected based on the tracking error signal. However, it is not possible to accurately detect the abnormal jump since the tracking error signal changes in a similar manner both when an abnormal jump occurs and when the address signal is being read.
Next, another conventional disk recording/reproduction device will be described with reference to FIG. 9.
First, the difference of the device illustrated in FIG. 9 from the device illustrated in FIG. 6 will be described. The device illustrated in FIG. 9 includes: an amplifier/filter 114 for amplifying a tracking error signal from the reproduced signal/servo signal detection circuit 104 so as to generate a wobble signal, and for detecting whether the track on the optical disk 102 being currently tracked is a land track or a groove track so as to generate a polarity signal indicating the detection result; a digitization circuit 115 for digitizing the output from the amplifier/filter 114; a phase/frequency comparator 117 for comparing the frequency or the phase of the wobble signal which has been digitized by the digitization circuit 115 with that of the clock signal from a voltage-controlled oscillator (hereinafter, referred to simply as the "VCO") 120 whose frequency has been divided by a frequency divider 129; a charge pump 128 for converting the signal from the phase/frequency comparator 117 indicating the comparison result to an analog value; a low pass filter 119 for integrating the output from the charge pump 128; the VCO 120 for generating a clock signal having a frequency which corresponds to the integrated voltage output from the low pass filter 119; the frequency divider 129 for dividing the frequency of the clock signal from the VCO 120; and a clock frequency divider 127 for dividing the frequency of the reference clock signal from the reference clock generator 111 and the frequency of the clock signal from the VCO 120.
The operation of the device having such a structure for reproducing/recording data from/to the optical disk 102 will be described with reference to the timing diagrams of FIGS. 10A to 10I.
The reproduced signal/servo signal detection circuit 104 receives the output signal from the optical head 103. Based on the output signal, the reproduced signal/servo signal detection circuit 104 generates and outputs a reproduced signal, as illustrated in FIG. 10A, and a tracking error signal, as illustrated in FIG. 10B.
The amplifier/filter 114 removes a high-frequency address signal from the tracking error signal so as to output a wobble signal. The amplifier/filter 114 also outputs a polarity signal indicating whether the track on the optical disk 102 being currently tracked is a land track or a groove track. The digitization circuit 115 digitizes the wobble signal, determines the polarity of the digitized wobble signal based on the polarity signal, and outputs the digitized wobble signal, as illustrated in FIG. 10C. The digitized wobble signal is provided to the phase/frequency comparator 117 in the PLL circuit (including the phase/frequency comparator 117, the charge pump 128, the low pass filter 119, the VCO 120 and the frequency divider 129). A synchronization clock signal which is synchronized with the wobble signal is obtained as an output of the PLL circuit. The frequency of the synchronization clock signal is divided by the clock frequency divider 127, thereby obtaining the frequency-divided synchronization clock signal, as illustrated in FIG. 10D. The frequency-divided synchronization clock signal is provided to the focusing/tracking control section 110, which controls the rotation of the motor. The focusing/tracking control section 110 controls the motor using the frequency-divided reference clock signal and the frequency-divided synchronization clock signal.
The device of FIG. 9 performs a data reproduction/recording operation using the reference clock signal in a manner similar to that of the device of FIG. 6.
When reproducing data, in order to read the address of the target sector K, the read gate signal of FIG. 10E is activated at a timing (e)-1 based on the address detection signal which has been output for the sector previous to the target sector K. The read gate signal is used as, for example, a start signal for a synchronization operation of the PLL circuit, which is provided in the reproduced signal digitization circuit 105. In response to the read gate signal, the PLL circuit in the reproduced signal digitization circuit 105 starts a synchronization operation for the digitized reproduced signal, and outputs to the demodulator 106 a digitized reproduced signal and a read clock signal which is synchronized with the reproduced signal. The demodulator 106 demodulates the digitized reproduced signal from the PLL circuit based on the read clock signal therefrom.
The demodulated address signal is sent to the error corrector/address detector 123. The error corrector/address detector 123 detects the address by the reference clock signal. When the address is normally detected, the error corrector/address detector 123 generates and outputs an address detection signal, as illustrated in FIG. 10G. Based on the address detection signal, the gate signal generator 112 activates gain the read gate signal at a timing (e)-2 of FIG. 10E in order to perform a read out operation for data recorded following the address region.
A reproduction operation for recorded data begins when the read gate signal is activated, and the synchronization operation of the PLL circuit in the reproduced signal digitization circuit 105 is started in response to the activation. As described above, the PLL circuit in the reproduced signal digitization circuit 105 performs a synchronization operation for the digitized reproduced signal and outputs to the demodulator 106 the digitized reproduced signal and the read clock signal which is synchronized with the reproduced signal. The demodulator 106 performs a demodulation operation in a manner similar to that described above. The demodulated reproduced data is sent to the error corrector/address detector 123 in synchronization with the reference clock signal. The error corrector/address detector 123 performs error correction for the reproduced data by the reference clock signal.
Next, the data recording operation of this device will be described.
In the following description, it is assumed that data is to be recorded to the target sector L.
The modulator 109 modulates recording data, which is obtained by adding an error correction code to the data to be recorded.
In order to read the address of the target sector L, the read gate signal of FIG. 10E is activated at a timing (e)-3 based on the address detection signal which has been output for the sector previous to the target sector L to which data is to now be recorded.
In response to the read gate signal, the PLL circuit in the reproduced signal digitization circuit 105 starts the synchronization operation for the digitized reproduced signal, so as to detect an address in a manner similar to that in the above-described data reproduction operation. Based on the address detection signal obtained when the address of the target sector L is detected, a modulator activation signal, as illustrated in FIG. 10, is activated at a timing (i)-1, whereby the modulation operation by the modulator 109 and the operation of the recording signal generation circuit 108 begin simultaneously. The recording gate signal of FIG. 10H is activated at a timing (h)-1 based on the address detection signal. In response to this, the laser drive circuit 107 optically modulates the laser light output from the optical head 103 based on the signal from the recording signal generation circuit 108 so as to record data to the sector L.
However, in the device having such a structure, the synchronization clock signal is used only for controlling the rotation of the motor 101, but is not used as a clock signal for the recording/reproduction operation. Therefore, as in the conventional device of FIG. 6, the data recording/reproduction operation cannot be performed until the number of rotations of the disk reaches the predetermined number of rotations.
As described above, the conventional device for recording/reproducing data to/from an optical disk has the following problems.
(1) The recording/reproducing operation cannot be performed while the number of rotations of the optical disk is not matched with the predetermined number of rotations.
(2) Since an address region is provided to be over a groove track and a land track, the tracking error signal changes in a similar manner both when the address region is being scanned by the optical head and when an abnormal jump of the optical head occurs. Therefore, at least when the address region is being scanned, it is not possible to detect the abnormal jump of the optical head based on the tracking error signal. Moreover, an abnormal jump may possibly misdetected due to variation in a wobble signal.